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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
January 2000
ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
General Description
The ACE1202 (Arithmetic Controller Engine) is a dedicated programmable monolithic integrated circuit for applications requiring high performance, low power, and small size. It is a fully static part fabricated using CMOS technology. The ACE1202 has an 8-bit microcontroller core, 64 bytes of RAM, 64 bytes of data EEPROM and 2K bytes of code EEPROM. Its onchip peripherals include a multi-function 16-bit timer, watchdog/ idle timer, and programmable undervoltage detection circuitry. On-chip clock and reset functions reduce the number of required external components. The ACE1202 is available in 8- and 14-pin SO and DIP packages. I 16-bit multifunction timer with difference capture I On-chip oscillator -- No external components -- 1s instruction cycle time I Instruction set geared for block encryption I On-chip power on reset I Programmable read and write disable functions I Memory mapped I/O I Multilevel Low Voltage Detection I Fully static CMOS -- Low power HALT mode (100nA @3.3V) -- Single supply operation (2.0-5.5V, 2.2-5.5V, 2.7-5.5V) I Software selectable I/O options -- Push-pull outputs with tri-state option -- Weak pull-up or high impedance inputs I 40 years data retention I 1,000,000 data changes I Packages available: 8- and 14-pin SO, 8- and 14-pin DIP I In-circuit programming
Features
I Arithmetic Controller Engine I 2K bytes on-board code EEPROM I 64 bytes data EEPROM I 64 bytes RAM I Watchdog I Multi-input wake-up on all I/O pins
Block and Connection Diagram
VCC GND External Reset
* 100nf Decoupling capacitor recommended
Power-on Reset Low Battery/Brown-out Detect
Internal Oscillator Watchdog/ 12-Bit Timer 0 16-Bit Timer 1 with Difference Capture HALT Power saving Mode RAM block 64 bytes 64 bytes of DATA EEPROM
G0 (CKO) G1 (CKI) G2 (T1) G3(Input only) G4 G5 G6 G7
G port general purpose I/O with multiinput wakeup
ACEx Control Unit Programming Interface 2K bytes of CODE EEPROM
(c) 1999 Fairchild Semiconductor Corporation ACE1202 Rev. E.1
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Absolute Maximum Ratings
Ambient Storage Temperature Input Voltage not including G3 G3 Input Voltage Lead Temperature (10s max) Electrostatic Discharge on all pins -65C to +150C -0.3V to VCC+0.3V 0.3V to 13V +300C 2000V min
Operating Conditions
Ambient Operating Temperature: ACE1202 ACE1202E Operating Supply Voltage: From -40C to 85C: See table for EEPROM write limits Relative Humidity (non-condensing) 95% 0C to 70C -40C to +85C 2.2V to 5.5V
ACE1202 DC Electrical Characteristics for VCC = 2.2 to 5.5V
All measurements valid for ambient operating temperature range unless otherwise stated.
Symbol
ICC
Parameter
Supply Current - no EEPROM write in progress HALT Mode current 2.2V 3.3V 5.5V
Conditions
MIN
TYP
0.5 1.0 1.6 10 200 50 400 350 1200 120 100
MAX
1.0 1.5 2.0 100 1000 1000 2500 5000 8000 250 150 5.5
Units
mA mA mA nA nA nA nA nA nA A* A* V
ICCH
3.3V, -40C to 25C 5.5V, -40C to 25C 3.3V, 25C to +85C 5.5V, 25C to +85C 3.3V, -40C to +125C 5.5V, -40C to +125C 5.5V 3.3V Code EEPROM in Programming Mode Data EEPROM in Operating Mode 4.5
ICCI VCCW
IDLE Mode Current EEPROM Write Voltage
5.0
2.4 1s/V 0.8VCC
5.5 10ms/V
V
SVCC VIH VIL IIP ITL VOL
Power Supply Slope Inputs Logic High Logic Low Input Pull-up Current TRI-STATE Leakage Output Low Voltage - VOL G0, G1, G2, G4, G6, G7 G5 VCC=5.5V, VIN=0V VCC=5.5V VCC= 3.3V - 5.5V 5.0 mA sink 10.0 mA sink VCC= 2.2V - 3.3V 3.0 mA sink 5.0 mA sink
0.2 VCC 30 65 2 350 200 0.2 VCC 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC 0.8 VCC 0.8 VCC 0.8 VCC
V V A nA V V V V V V V V
VOH
Output High Voltage - VOH G0, G1, G2, G4, G6, G7 G5
VCC= 3.3V - 5.5V 0.4 mA source 1.0 mA source VCC= 2.2V - 3.3V 0.4 mA source 0.8 mA source
* Based on continuous IDLE looping.
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Preliminary ACE1202 AC Electrical Characteristics for VCC = 2.2 to 5.5V
Parameter
Instruction cycle time from internal clock - setpoint Internal clock voltage dependent frequency variation Internal clock temperature dependent frequency variation Internal clock frequency deviation for 0.5V drop Crystal oscillator frequency External clock frequency EEPROM write time Internal clock start up time Oscillator start up time (Note 2) (Note 2)
Conditions
5.0V at 25C 3.0V to 5.5V, constant temperature 3.0V to 5.5V, full temperature range 3.0V to 4.5V for ACE1202E, T=constant (Note 1) (Note 2)
MIN
0.9
TYP
1.00
MAX
1.1 5% 10% 2% 4 4
Units
s
MHz MHz ms ms cycles
3
10 2 2400
Note 1: The maximum permissible frequency is guaranteed by design but not 100% tested. Note 2: The parameter is guaranteed by design but not 100% tested.
ACE1202 Electrical Characteristics for programming
All data valid at ambient temperature between 4.5V and 5.5V. See "EEPROM write time" in the AC characteristics for definition of the programming ready time. The following characteristics are guaranteed by design but are not 100% tested. Parameter
tHI tLO tDIS tDIH tDOS tDOH tSV1, tSV2 tLOAD1, tLOAD2, tLOAD3, tLOAD4 VSUPERVOLTAGE
Description
CLOCK high time CLOCK low time SHIFT_IN setup time SHIFT_IN hold time SHIFT_OUT setup time SHIFT_OUT hold time LOAD supervoltage timing LOAD timing Supervoltage level
MIN
500 500 100 100 100 900 50 5 11.5
MAX
DC DC
Units
ns ns ns ns ns ns us us
12.5
V
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Absolute Maximum Ratings
Ambient Storage Temperature Input Voltage not including G3 G3 Input Voltage Lead Temperature (10s max) Electrostatic Discharge on all pins -65C to +150C -0.3V to VCC+0.3V 0.3V to 13V +300C 2000V min
Operating Conditions
Ambient Operating Temperature: ACE1202B ACE1202BE ACE1202BV Operating Supply Voltage: From -40C to 125C: See table for EEPROM write limits Relative Humidity (non-condensing) 95% 0C to 70C -40C to +85C -40C to +125C 2.7V to 5.5V
ACE1202B DC Electrical Characteristics for VCC = 2.7 to 5.5V
All measurements valid for ambient operating temperature range unless otherwise stated.
Symbol
ICC
Parameter
Supply Current - no EEPROM write in progress HALT Mode current 2.7V 3.3V 5.5V
Conditions
MIN
TYP
0.7 1.0 1.6 10 200 50 400 350 1200 120 100
MAX
1.2 1.5 2.0 100 1000 1000 2500 5000 8000 250 150 5.5
Units
mA mA mA nA nA nA nA nA nA A* A* V
ICCH
3.3V, -40C to 25C 5.5V, -40C to 25C 3.3V, 25C to +85C 5.5V, 25C to +85C 3.3V, -40C to +125C 5.5V, -40C to +125C 5.5V 3.3V Code EEPROM in Programming Mode Data EEPROM in Operating Mode 4.5
ICCI VCCW
IDLE Mode Current EEPROM Write Voltage
5.0
2.7 1s/V 0.8VCC
5.5 10ms/V
V
SVCC VIH VIL IIP ITL VOL
Power Supply Slope Inputs Logic High Logic Low Input Pull-up Current TRI-STATE Leakage Output Low Voltage - VOL G0, G1, G2, G4, G6, G7 G5 VCC=5.5V, VIN=0V VCC=5.5V VCC= 3.3V - 5.5V 5.0 mA sink 10.0 mA sink VCC= 2.7V - 3.3V 3.0 mA sink 5.0 mA sink
0.2 VCC 30 65 2 350 200 0.2 VCC 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC 0.8 VCC 0.8 VCC 0.8 VCC
V V A nA V V V V V V V V
VOH
Output High Voltage - VOH G0, G1, G2, G4, G6, G7 G5
VCC= 3.3V - 5.5V 0.4 mA source 1.0 mA source VCC= 2.7V - 3.3V 0.4 mA source 0.8 mA source
* Based on continuous IDLE looping.
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Preliminary ACE1202B AC Electrical Characteristics for VCC = 2.7 to 5.5V
Parameter
Instruction cycle time from internal clock - setpoint Internal clock voltage dependent frequency variation Internal clock temperature dependent frequency variation Internal clock frequency deviation for 0.5V drop Crystal oscillator frequency External clock frequency EEPROM write time Internal clock start up time Oscillator start up time (Note 2) (Note 2)
Conditions
5.0V at 25C 3.0V to 5.5V, constant temperature 3.0V to 5.5V, full temperature range 3.0V to 4.5V for ACE1202BE, T=constant (Note 1) (Note 2)
MIN
0.9
TYP
1.00
MAX
1.1 5% 10% 2% 4 4
Units
s
MHz MHz ms ms cycles
3
10 2 2400
Note 1: The maximum permissible frequency is guaranteed by design but not 100% tested. Note 2: The parameter is guaranteed by design but not 100% tested.
ACE1202B Electrical Characteristics for programming
All data valid at ambient temperature between 4.5V and 5.5V. See "EEPROM write time" in the AC characteristics for definition of the programming ready time. The following characteristics are guaranteed by design but are not 100% tested. Parameter
tHI tLO tDIS tDIH tDOS tDOH tSV1, tSV2 tLOAD1, tLOAD2, tLOAD3, tLOAD4 VSUPERVOLTAGE
Description
CLOCK high time CLOCK low time SHIFT_IN setup time SHIFT_IN hold time SHIFT_OUT setup time SHIFT_OUT hold time LOAD supervoltage timing LOAD timing Supervoltage level
MIN
500 500 100 100 100 900 50 5 11.5
MAX
DC DC
Units
ns ns ns ns ns ns us us
12.5
V
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Absolute Maximum Ratings
Ambient Storage Temperature Input Voltage not including G3 G3 Input Voltage Lead Temperature (10s max) Electrostatic Discharge on all pins -65C to +150C -0.3V to Vcc+0.3V 0.3V to 13V +300C 2000V min
Operating Conditions
Operating Supply Voltage excluding EEPROM write: 0C to +70C 2.0V to 5.5V (based on preliminary data) Relative Humidity (non-condensing) 95%
Preliminary ACE1202L DC Electrical Characteristics for VCC = 2.0 to 5.5V
All measurements valid for ambient operating temperature range unless otherwise stated.
Symbol
ICC
Parameter
Supply Current - no EEPROM write in progress HALT Mode Current IDLE Mode Current EEPROM Write Voltage Power Supply Slope Inputs Logic High Logic Low Input Pull-up Current TRI-STATE Leakage Output Low Voltage G0, G1, G2, G4, G6, G7 G5 G0, G1, G2, G4, G6, G7 G5 2.0V
Conditions
MIN
TYP
0.4
MAX
0.5
Units
mA
ICCH ICCI VCCW SVCC VIH VIL IIP ITL VOL
2.0V, 0C to 70C 2.0V Write Not Allowed for VCC < 2.4V 1us/V 0.8 VCC
10 30
100 50
nA A V
10ms/V V V A nA V V V V V V V V
0.2 VCC VCC=5.5V, VIN=0V VCC=5.5V VCC= 3.3V - 5.5V 5.0 mA sink 10.0 mA sink VCC= 2.0V - 3.3V 0.8 mA sink 10.0 mA sink VCC= 3.3V - 5.5V 0.4 mA source 1.0 mA source VCC= 2.0V - 3.3V 0.1 mA source 0.2 mA source 0.8 VCC 0.8 VCC 1.44 VCC 1.44 VCC 30 65 2 350 200 0.2 VCC 0.2 VCC 0.36 VCC 0.36 VCC
VOH
Output High Voltage G0, G1, G2, G4, G6, G7 G5 G0, G1, G2, G4, G6, G7 G5
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Preliminary ACE1202L AC Electrical Characteristics for VCC = 2.0 to 5.5V
Parameter
Instruction cycle time from internal clock - setpoint Internal clock voltage dependent frequency variation Internal clock temperature dependent frequency variation Internal clock frequency deviation for 0.5V drop Crystal oscillator frequency External clock frequency EEPROM write time Internal clock start up time Oscillator start up time (Note 2) (Note 2)
Conditions
5.0V at 25C 3.0V to 5.5V, constant temperature 3.0V to 5.5V, full temperature range 3.0V to 4.5V for ACE1202E, T=constant (Note 1) (Note 2)
MIN
0.9
TYP
1.00
MAX
1.1 5% 10% 2% 4 4
Units
s
MHz MHz ms ms cycles
5
10 2 2400
Note 1: The maximum permissible frequency is guaranteed by design but not 100% tested. Note 2: The parameter is guaranteed by design but not 100% tested.
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
3.0
ACE1202 AC & DC Characteristic Graphs
The graphs in this section are for design guidance and are based on prelimintest data Figure 2: RC Oscillator Frequency (VCC=5.0V)
2.600 2.400 2.200 2.000 1.800 1.600 1.400 1.200 1.000 3.3k/82pF 5.6k/100pF 6.8K/100pF Resistor & Capacitor Values [k & pF]
Frequency (MHz)
Avg Min Max
Figure 3: RC Oscillator Frequency (VCC=2.5V)
1.600
Frequency (MHz)
1.400 1.200 1.000 0.800 0.600 3.3k/82pF 5.6k/100pF 6.8K/100pF Resistor & Capacitor Values [k & pF]
Avg Min Max
Figure 4: Internal Oscillator Frequency
2200
Frequency (KHz)
5.0V 5.5V
2000
4.5V
1800 1600 -45 -5 25 90 130
Temperature [C]
4.0V 3.5v 2.2V
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Figure 5: Power Supply Rise Time
VCC
VBATT
1V
tS min
tS actual
tS max
time
Name
VCC VBATT tS min tS actual tS max SVCC Supply Voltage
Parameter
Battery Voltage (Nominal Operating Voltage) Minimum Time for VCC to Rise by 1V Actual Time for VCC to Rise by 1V Maximum Time for VCC to Rise by 1V Power Supply Slope
Unit
[V] [V] [ms] [ms] [ms] [ms/V]
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Figure 6: ICC Active
0.520 0.500 0.480 0.460 0.440 0.420 0.400 0.380 130 95 25 -5 -20 -45 Temperature [C]
Current (mA)
Vcc=3.0V
1.110 1.100 1.090 1.080 1.070 1.060 1.050 1.040 130 95 25 -5 -20 -45 Temperature [C]
Current (mA)
Vcc=4.5V
1.340
Current (mA)
1.320 1.300 1.280 1.260 1.240 130 95 25 -5 -20 -45 Temperature [C]
Vcc=5.0V
1.600 1.580 1.560 1.540 1.520 1.500 1.480 1.460 1.440 130 95 25 -5 -20 -45 Temperature [C]
Current (mA)
Vcc=5.5V
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Figure 7: HALT Current
350
HALT Current (nA)
300 250 200 150 100 50 0 130 95 25 -5 Temperature [C]
Vcc=3.3V
1400
HALT Current (nA)
1200 1000 800 600 400 200 0 130 95 25 -5 Temperature [C] Vcc=5.5V
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Figure 8: ACE1202 Application Example (Remote Keyless Entry)
VCC Optional LED G4 G0 G1 GND VCC G3 G5 G2 RF Stage RF Interface
Figure 9: ACE1202 Pinout - Normal Operation
G3 G4 NC G6 G7 G5 G0
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC GND NC G2 NC RESET G1
G3 G4 G5 G0
1 2 3 4
8 7 6 5
VCC GND G2 G1
Figure 10: ACE1202 Pinout - Programming Mode
1 2 3 4 5 6 7 14 13 12 11 10 9 8
LOAD SFT_I NC G6 G7 G5 GO
VCC GND NC SFT_O NC RESET CKI
LOAD SFT_I G5 GO
1 2 3 4
8 7 6 5
VCC GND SFT_O CKI
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
4.0 Arithmetic Controller Core
The ACE1202 core is specifically designed for low cost applications involving bit manipulation, shifting and block encryption. It is based on a modified Harvard architecture meaning peripheral, I/O, and RAM locations are addressed separately from instruction data. The core differs from the traditional Harvard architecture by aligning the data and instruction memory sequentially. This allows the X-pointer (12-bits) to point to any memory location in either
segment of the memory map. This modification improves the overall code efficiency of the ACE1202 and takes advantage of the flexibility found on Von Neumann style machines.
4.1 CPU Registers
The ACE1202 has five general purpose registers. They are the A, X, PC, SP, and SR. The X, SP and SR are memory mapped registers.
Figure 11: Programming Model
A X PC SP SR 11 10
7
0 0 0 3 0
8-bit accumulator register 12-bit X pointer register 11-bit program counter 4-bit stack pointer 8-bit status register NEGATIVE flag HALF CARRY flag (from bit 3) CARRY flag (from MSB) ZERO flag GLOBAL Interrupt Mask READY flag (from EEPROM)
R 0 0GZCHN
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
4.1.1 Accumulator
Accumulator A is general-purpose 8-bit register that holds operands and results of arithmetic calculations or data manipulations.
Zero (Z)
The Z bit is set if the result of an arithmetic, logic, or data manipulation operation is zero. Otherwise, the Z bit is cleared.
4.1.2 X Pointer
The X register provides an 12-bit indexing value that can be added to an 8-bit offset provided in an instruction to create an effective address. The X register can also be used as a counter or as a temporary storage register.
Negative (N)
The N bit is set if the result of an arithmetic, logic, or data manipulation operation is negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be negative if its most significant bit (MSB) is a one.
Interrupt Mask (G)
The interrupt request mask (G) is a global mask that disables all maskable interrupt sources. Until the G bit is set, interrupts can become pending, but the operation of the CPU continues uninterrupted. After any reset, the G bit is cleared by default and can only be set by a software instruction. When an interrupt is recognized, the G bit is cleared after the PC is stacked and the interrupt vector is fetched. After the interrupt is serviced, a return from interrupt instruction is normally executed to restore the PC to the value that was present before the interrupt occurred. The G bit is set after a return from interrupt is executed. Although the G bit can be set within an interrupt service routine, "nesting" interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism.
4.1.3 Program Counter (PC)
The program counter, a 11-bit register, contains the address of the next instruction to be executed. After reset, the program counter is initialized to 0x800 in normal mode.
4.1.4 Stack Pointer (SP)
The ACE1202 has an automatic program stack. This stack can be initialized to any location between addresses 0x30-0x3F. By default, the stack is initialized to 0x3F. Normally, the SP is initialized by one of the first instructions in an application program. The stack is configured as a data structure that decrements from high memory to low memory. Each time a new address is pushed onto the stack, the SP is decremented by two. Each time an address is pulled from the stack, the SP is incremented by two. At any given time, the SP points to the next free location in the stack. When a subroutine is called by a jump to subroutine (JSR), the address of the instruction, after the JSR instruction, is automatically pushed onto the stack least significant byte first. When the subroutine is finished, a return from subroutine (RET) instruction is executed. The RET pulls the previously stacked return address from the stack, and loads it into the program counter. Execution then continues at this recovered return address.
4.2 Interrupt handling
When an interrupt is recognized, the current instruction completes its execution. The return address (the current value in the program counter) is pushed onto the stack and execution continues at the address specified by the unique interrupt vector (see Table 9). This process takes five instruction cycles. At the end of the interrupt service routine, a RETI instruction is executed. The RETI instruction causes the saved address to be pulled off the stack in reverse order. The G bit is set and program execution resumes at the return address. The ACE1202 is capable of supporting four interrupts. Three are maskable through the G bit of the Status register and the fourth (software interrupt) is not inhibited by the G bit (see Figure 12). (See Table 6 for the interrupt priority sequence.) The software interrupt instruction is executed in a manner similar to other maskable interrupts in that the program counter registers are stacked. However, with a software interrupt, the G bit is not effected. This means, when returning from a software interrupt, a RET instruction should be used rather than using the RETI instruction. The RETI instruction will set the G bit.
4.1.5 Status Register (SR)
This 8-bit register contains four condition code indicators (C, H, Z, and N), one interrupt masking bit (G), and an EEPROM write flag (R). In the ACE1202, condition codes are automatically updated by most instructions.
Carry/Borrow (C)
The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an arithmetic operation. The rotate instruction operates with and through the carry bit to facilitate multiple-word shift operations. The LDC and INVC instructions facilitate direct bit manipulation using the carry flag.
4.3 Addressing Modes
The ACE1202 has seven addressing modes.
Half Carry (H)
The half carry flag indicates whether an overflow has taken place on the boundary between the two nibbles in the accumulator. It is primarily used for BCD arithmetic calculation.
Indexed
In this addressing mode, a 8-bit unsigned offset value is added to the X-pointer yielding a new effective address. This mode can be used to address any memory location (Instruction or Data).
Indirect Table 6: Interrupt Priority Sequence Interrupt
MIW Timer0 Timer1 Software This is the "normal" addressing mode. The operand is the data memory addressed by the X-pointer.
Priority (4 highest, 1 lowest)
4 3 2 1
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Figure 12: ACE1202 Basic Interrupt Structure
Int. Source & Priority SW
T1
T0
MiWu
GIE Int. Pend. Flags Int. Enable Bits Global Int. Enable
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Direct
The instruction contains an 8-bit address field that directly points to the data memory for the operand.
Absolute
This mode is used with the JMP and JSR instructions, with the instruction field replacing the 11-bits in the program counter. This allows jumping to any location in the memory map.
Immediate
The instruction contains an 8-bit immediate field as the operand.
Relative
This mode is used for the JP and the bit manipulation instructions, where the instruction field being added to the program counter to get the new program location.
Inherent
This instruction has no operand associated with it.
Table 7: Instruction Addressing Modes Instruction
ADC ADD AND OR SUBC XOR CLR INC DEC IFEQ IFGT IFNE IFLT SC RC IFC IFNC INVC LDC STC RLC RRC LD ST LD NOP IFBIT SBIT RBIT JP JSR JMP RET RETI INTR A, [00,X] A, [00,X] no-op no-op no-op #, A #, M #, M #, M #, [X] #, [X] Rel M,M+1 M,M+1 A, # X, # M, # #, M #, M M M A, M A, M M, M no-op A, [00,X] A, [00,X] A, [X] A, [X] A A A, # A, # A, # X, # no-op no-op no-op no-op no-op X, # X, # M,#
Immediate
A, # A, # A, # A, # A, # A, #
Direct
A, M A, M A, M A, M A, M A, M M M M A, M A, M A, M
Indexed
Indirect
A, [X] A, [X] A, [X] A, [X] A, [X] A, [X] A A A X X X A, [X] A, [X] A, [X]
Inherent
Relative
Absolute
A, [00,X] A, [00,X] A, [00,X]
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Table 8: Instruction Addressing Modes
Mnemonic
ADC ADC ADC ADD ADD ADD AND AND AND CLR CLR CLR DEC DEC DEC IFBIT IFBIT IFC IFEQ IFEQ IFEQ IFEQ IFEQ IFEQ IFGT IFGT IFGT IFGT IFGT IFNE IFNE IFNE IFNE IFLT IFNC INC INC INC INTR INVC A M X A, [00,X] A, [X] A, # A, M M, # X, # A, # A, [00,X] A, [X] A, M X, # A, # A, [00,X] A, [X] A, M X, #
Operand
A, [X] A, M A, # A, [X] A, M A, # A, # A, M A, [X] X A M A M X #, A #, M
Bytes
1 2 2 1 2 2 2 2 1 1 1 2 1 2 1 1 2 1 2 1 2 2 3 3 2 2 1 2 3 2 2 1 2 3 1 1 2 1 1 1
Cycles
1 2 2 1 2 2 2 2 1 1 1 1 1 2 1 1 2 1 2 1 2 2 3 3 2 2 1 2 3 2 2 1 2 3 1 1 2 1 5 1
Flags affected
C,H,Z,N C,H,Z,N C,H,Z,N Z,N Z,N Z,N Z,N Z,N Z,N Z C,Z,N C,Z,N Z,N Z,N Z None None None None None None None None None None None None None None None None None None None None Z,N Z,N Z None C
Mnemonic
JMP JMP JP JSR JSR LD LD LD LD LD LD LDC LD NOP OR OR OR RBIT RBIT RC RET RETI RLC RLC RRC RRC SBIT SBIT SC ST ST ST STC SUBC SUBC SUBC XOR XOR XOR
Operand
[00,X] M, M+1 M, M+1 [00,X] A, # A, [00,X] A, [X] A, M M, # X, # #, M M, M A, # A, [X] A, M #, [X] #, M
Bytes
2 3 1 3 2 2 2 1 2 3 3 2 3 1 2 1 2 1 2 1 1 1
Cycles
3 4 1 5 5 2 3 1 2 3 3 2 3 1 2 1 2 2 2 1 5 5 1 2 1 2 2 2 1 3 1 2 2 2 1 2 2 1 2
Flags affected
None None None None None None None None None None None C None None Z,N Z,N Z,N Z,N Z,N C None None C,Z,N C,Z,N C,Z,N C,Z,N Z,N Z,N C None None None Z,N C,H,Z,N C,H,Z,N C,H,Z,N Z,N Z,N Z,N
A M A M #, [X] #, M A, [00,X] A, [X] A, M #, M A, # A, [X] A, M A, # A, [X] A, M
1 2 1 2 1 2 1 2 1 2 2 2 1 2 2 1 2
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4.4 Memory Map
All I/O ports, peripheral registers and core registers, except the accumulator and the program counter are mapped into memory space.
Table 9: Memory Map Address
0x00 - 0x3F 0x40 - 0x7F 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 - 0xBC 0xBD 0xBE 0xBF 0xC0 0xCE 0xCF 0x800 - 0xFF5 0xFF6 - 0xFF7 0xFF8 - 0xFF9 0xFFA - 0xFFB 0xFFC - 0xFFD 0xFFE - 0xFFF LBD Core Core Core Core Core Code EEPROM/ROM Core Core Core Core
Block
SRAM Data EEPROM Timer1 Timer1 Timer1 Timer1 Timer1 MIWU MIWU MIWU I/O I/O I/O Timer0 Timer0 Clock
Contents
Data RAM Non-volatile parameters T1RALO register T1RAHI register TMR1LO register TMR1HI register T1CNTRL register WKEDG register WKPND register WKEN register PORTGD register PORTGC register PORTGP register WDSVR register T0CNTRL register HALT mode register Reserved LBD register XHI register XLO register Power mode clear (PMC) register SP register Status register Instruction data Timer0 Interrupt vector Timer1 Interrupt vector MIWU Interrupt vector Software Interrupt vector Reserved
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4.5 Memory
The ACE1202 device has 64 bytes of SRAM and 64 bytes of EEPROM available for data storage. The microcontroller also has a 2K byte EEPROM block for program storage. The user can read/ write to RAM and data EEPROM but cannot perform writes to the 2K byte EEPROM array which is protected from writes during normal mode operations. The instruction data in the program EEPROM array can only be rewritten when the device is in program mode and if the initialization register bit WDIS (write disable) is not set. While in normal mode, the user can write to the data EEPROM array by 1) polling the R bit of the status register, then 2) executing the appropriate write instruction. A "1" on the R bit indicates the data EEPROM block is ready to perform the next write. A "0" indicates the data EEPROM is busy. The data EEPROM array will
reset the R bit on the completion of a write cycle. Attempts to read, write, or enter HALT while the data EEPROM is busy (R bit = "0") could affect the current data being written.
4.6 Initialization Registers
The ACE1202 has two 8-bit wide initialization registers. These registers are read from memory space on power-up and initializes certain on-chip peripherals. Figure 13 provides a detailed description of Initialization Register 1. The Initialization Register 2 is used to trim the internal oscillator. This register is pre-programmed in the factory to yield a 1MHz internal clock. Both Initialization Registers 1 and 2 are read/writable in programming mode. However, retrimming the internal oscillator (writing to the Initialization Register 2) is discouraged.
Figure 13: Initialization Register 1 Bit 7
CMODE0 (0) RDIS (1) WDIS (2) UBD (3) LBDEN (4) BOREN (5) WDEN (6) CMODE1 (7) CMODE0
Bit 6
CMODE1
Bit 5
WDEN
Bit 4
BOREN
Bit 3
LBDEN
Bit 2
UBD
Bit 1
WDIS
Bit 0
RDIS
If set, disables attempts to read any EEPROM contents in programming mode If set, disables attempts to write any EEPROM contents in programming mode If set, the device will not allow writes to occur in the upper block of data EEPROM 1 enables LBD, 0 disables LBD If set, allows a brown-out reset to occur if Vcc is so low that a reliable EEPROM write cannot take place If set, enables the on-chip processor watchdog circuit Clock mode select bit one Clock mode select bit zero
Note 1: If WDIS and RDIS bits are both set, the device will no longer be able to be placed into program mode. Note 2: If the RDIS or UBD bits are not set while the WDIS bit is not set, then the RDIS and UBD bits could be reset.
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5.0 Timer 1
Timer1 is a versatile 16-bit timer which can operate in one of four modes: * Pulse Width Modulation (PWM) mode, which generates pulses of a specified width and duty cycle * External Event Counter mode, which counts occurrences of an external event * Standard Input Capture mode, which measures the elapsed time between occurrences of external events * Difference Input Capture mode, which automatically measure the difference between edges. Timer1 contains a 16-bit timer (counter) register, designated TMR1, and one 16-bit autoreload (capture) register, designated T1RA. These 16-bit registers are organized as a pair of 8-bit memory mapped register bytes, TMR1HI and TMR1LO, and T1RAHI and T1RALO. The timer (counter) block uses one I/O pin, designated T1, which is the alternate function of G2.
The timer can be started or stopped under program control. When running, the timer counts down (decrements). Depending on the operating mode, the timer counts either instruction clock cycles or transitions on the T1 pin. Occurrences of timer underflows (transitions from 0x0000 to 0xFFFF) can either generate an interrupt and/or toggle the T1 pin, also depending on the operating mode. There is one interrupt associated with the timer, designated the Timer1 interrupt. When timer interrupt is enabled, the source of the interrupt depends on the timer operating mode: either a timer underflow, or a transfer of data to or from the T1RA register. By default, the timer register is reset to FFFF and the reload register is reset to 0000.
5.1 Timer control bits
Timer1 is controlled by reading and writing to the T1CNTRL register. By programming the control bits, the user can enable or disable the timer interrupts, set the operating mode, and start or stop the timer. The control bits operate as described in Tables 10 and 11.
Table 10: TIMER1 Control Register Bits T1CNTRL Register
Bit 7 Bit 6 Bit 5 Bit 4
Name
T1C3 T1C2 T1C1 T1C0
Function
Timer TIMER1 control bit 3 (see Table 11) Timer TIMER1 control bit 2 (see Table 11) Timer TIMER1 control bit 1 (see Table 11) Timer TIMER1 run: 1 = Start timer, 0 = Stop timer; or Timer TIMER1 underflow interrupt pending flag in input capture or difference capture modes Timer1 interrupt pending flag: 1 = Timer1 interrupt pending, 0 = Timer1 interrupt not pending Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled, 0 = Timer1 interrupt disabled Selects capture types 0 = Pulse capture 1 = Cycle capture Reserved
Bit 3 Bit 2 Bit 1
T1PNDA T1ENA M4S1
Bit 0
-----------
Table 11: Timer Operating Modes T1 C3
0 0 1 1 0 0 1 1 1 1
T1 C2
0 0 0 0 1 1 1 1 1 1
T1 C1
0 1 1 0 0 1 0 0 1 1
M4 S1
x x x x x x 0 1 0 1 MODE 2 MODE 2
Timer Mode Source
Interrupt A
Timer Underflow Timer Underflow Autoreload T1RA Autoreload T1RA Pos. T1A Edge Neg. T1A Edge Pos. to Neg. Pos. to Pos. Neg. to Pos. Neg. to Neg.
Timer Counts On
T1A Pos. Edge T1A Neg. Edge Instruction Clock Instruction Clock Instruction Clock Instruction Clock Instruction Clock Instruction Clock Instruction Clock Instruction Clock
MODE 1 T1A Toggle MODE 1 No T1A Toggle MODE 3 Captures: T1A Pos. Edge MODE 3 Captures: T1A Neg. Edge MODE 4 Difference Capture MODE 4 Difference Capture MODE 4 Difference Capture MODE 4 Difference Capture
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5.2 Mode 1: Pulse Width Modulation Mode
In the Pulse Width Modulation (PWM) mode, the timer counts down at the instruction clock rate. When an underflow occurs, the timer register is reloaded from T1RA, and decrementing proceeds from the loaded value. At every underflow interrupt, software should load the T1RA register with the alternate PWM value. The timer can be configured to toggle the T1 output bit upon underflow. This results in the generation of a clock signal on T1 with the width and duty cycle controlled by the values stored in the T1RA. A block diagram of the timer operating in the PWM mode is shown In Figure 14. There is one interrupt associated with the timer, designated the Timer1 interrupt. The interrupt is maskable by the enable bit T1EN. T1 will generate an interrupt with every timer underflow if the timer interrupt is enabled by T1EN. The interrupt will be simultaneous with every rising and falling edge of the PWM output. Generating interrupts only on rising-, or falling edges of T1 is achievable through appropriate handling of T1EN by the user software. When an underflow occurs that causes a timer reload from T1RA, the interrupt pending flag bit T1PNDA is set. A CPU interrupt occurs if T1EN bit and the G (Global Interrupt enable) bit of the Status register is set. The interrupt service routine must reset the pending bit and perform whatever processing is necessary at the interrupt point.
The following steps can be used to operate the timer in the PWM mode. In this example, the T1 output pin is toggled with every timer underflow, and the "high" and "low" times for the T1 output can be set to different values. The T1 output can start out either high or low; the instructions below are for starting with the T1 output high. (Follow the instructions in parentheses to start the T1 output low.) 1. Configure the T1 pin as an output by setting bit 2 of PORTGC. 2. Initialize the T1 pin value to 1 (or 0) by setting (or clearing) bit 2 of PORTGD. 3. Load the PWM "high" or "low" time into the timer register. 4. Load the PWM "low" or "high" time into the T1RA register. 5. Write the appropriate value to the timer control bits T1C3T1C2- T1C1 to select the PWM mode, and to toggle the T1 output with every timer underflow (see Table 11). 6. Set the T1C0 bit to start the timer. 7. Upon every underflow interrupt load T1RA with alternate values, ON or OFF time. If the user wishes to generate an interrupt on timer output transitions, reset the pending flags and then enable the interrupt using T1EN. The G bit must also be set. The interrupt service routine must reset the pending flag and perform whatever processing is desired.
Figure 14: Pulse Width Modulation Mode
Timer Underflow Interrupts
16-bit Autoreload Register T1RA BUS T1 Data Latch 16-bit Timer
Instruction Clock
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5.3 Mode 2: External Event Counter Mode
The external event counter mode is similar to the PWM mode, except that instead of counting instruction clock pulses, the timer counts transitions received on the T1 pin (configured as an input). The T1 pin should be connected to an external device that generates a pulse for each event to be counted. The input signal on T1 must have a pulse width equal to or greater than one instruction cycle. The timer can be configured to sense either positive-going or negative-going transitions on the T1 pin. The maximum frequency at which transitions can be sensed is one-half the frequency of the instruction clock. As with the PWM mode, when an underflow occurs, the timer register is reloaded from the T1RA registers, and counting proceeds downward from the loaded value. A block diagram of the timer operating in the external event counter mode is shown in Figure 15. The following steps can be used to operate the timer in the external event counter mode. 1. Configure the T1 pin as an input by clearing bit 2 of PORTGC. 2. Load the initial count into the timer register and the T1RA
register. When this number of external events is detected, the counter will reach zero, however, it will not underflow until the next event is detected. To count N pulses, load the value N-1 into the registers. If it is only necessary to count the number of occurrences and no action needs to be taken at a particular count, load the value 0xFFFF into the registers. 3. In order to generate an interrupt each time the timer underflows, clear the T1PND pending flag and then enable the interrupt by setting the T1EN bit. The G bit must also be set. 4. Write the appropriate value to the timer control bits T1C3T1C2- T1C1 to select the external event counter mode, and to select the type of transition to be sensed on the T1 pin (positive-going or negative-going; see Table 11). 5. Set the T1C0 bit register to start the timer. If interrupts are being used, the Timer1 interrupt service routine must clear the T1PND flag and take whatever action is required when the timer underflows. If the user wishes to merely count the number of occurrences of an event, and anticipates that the number of events may exceed 65,536, the interrupt service routine should record the number of underflows by incrementing a counter in memory. On each underflow, the timer (counter) register is reloaded with the value from the T1RA register.
Figure 15: External Event Counter Mode
16-bit Autoreload Register T1RA Timer Underflow Interrupts T1 Edge Selector Logic 16-bit Timer (Counter)
BUS
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5.4 Mode 3: Input Capture Mode
In the input capture mode, the T1 pin is configured as input. The timer counts down at the instruction clock rate. A transition received on the T1 pin causes a transfer of the timer contents to the T1RA register. The input signal on T1 must have a pulse width equal to or greater than one instruction cycle. (Refer to the AC Electrical Specifications for this device.) The values captured in the T1RA register at different times reflect the elapsed time between transitions on the T1 pin. The input pin can be configured to sense either positive-going or negative-going transitions. A block diagram of the timer operating in the input capture mode is shown in Figure 16. There are two interrupt events associated with the input capture mode: input capture in T1RA and timer underflow. If interrupts are enabled, a Timer1 interrupt is triggered by either an input capture in T1RA or a timer underflow. In this operating mode, the T1C0 co ntrol bit serves as the timer underflow interrupt pending flag. The Timer1 interrupt service routine can look at this flag and the T1PND flag to determine what caused the interrupt. A set T1C0 flag means that a timer underflow occurred, whereas a set T1PND flag means that an input capture occurred in T1RA. It is possible that both flags will be found set, meaning that both events occurred at the same time. The interrupt routine should take this possibility into consideration. Because the T1C0 bit is used as the underflow interrupt pending flag, it is not available for use as a start/stop bit as in the other modes. The timer register counts down continuously at the instruction clock rate, starting from the time that the input capture mode is selected with bits T1C3-T1C2-T1C1. To stop the timer from running, you must change from the input capture mode to the PWM or external event counter mode and reset the T1C0 bit. The input pins can be independently configured to sense positivegoing or negative-going transitions, resulting in two possible input capture mode configurations. The edge sensitivity of pin T1 is controlled by bit T1C1 as indicated in Table 11. The edge sensitivity of a pin can be changed without leaving the input capture mode by setting or clearing the appropriate control bit (T1C1), even while the timer is running. This feature allows you to measure the width of a pulse received on an input pin. For example, the T1 pin can be programmed to be sensitive to a positive-going edge. When the positive edge is sensed, the timer contents are transferred to the T1RA register, and a Timer1 interrupt is generated. The Timer1
interrupt service routine records the contents of the T1RA register and also reprograms the input capture mode, changing the T1 pin from positive to negative edge sensitivity. When the negative-going edge appears on the T1 pin, another Timer1 interrupt is generated. The interrupt service routine reads the T1RA register again. The difference between the previous reading and the current reading reflects the elapsed time between the positive edge and negative edge on the T1 input pin, i.e., the width of the positive pulse. Remember that the Timer1 interrupt service routine must test the T1C0 and T1PND flags to determine what caused the interrupt. The software that measures elapsed time must take into account the possibility that an underflow occurred between the first and second readings. This can be managed by using the interrupt triggered by each underflow. The Timer1 interrupt service routine, after determining that an underflow caused the interrupt, should record the occurrence of an underflow by incrementing a counter in memory, or by some other means. The software that calculates the elapsed time should check the status of the underflow counter and take it into account in making the calculation. The following steps can be used to operate the timer in the input capture mode. 1. Configure the T1 pin as input by clearing bit 2 of PORTG2. 2. With the timer configured to operate in the PWM or external event counter mode (T1C2 equal to 0), reset the T1C0 bit. This stops the timer register from counting. 3. Load the initial count into the timer register, typically the value 0xFFFF to allow the maximum possible number of counts before underflow. 4. Clear the T1PND interrupt pending flag, then set the T1EN interrupt enable bit. The G bit should also be set. The interrupt is now enabled. 5. Write the appropriate value to the timer control bits T1C3T1C2- T1C1 to select the input capture mode, and to select the types of transitions to be sensed on the T1 pin (positivegoing or negative-going; see Table 11). As soon as the input capture mode is enabled, the timer starts counting. When the programmed type of edge is sensed on the T1 pin, the T1RA register is loaded and a Timer1 interrupt is triggered. A Timer1 interrupt is also triggered when an underflow occurs in the timer register. The interrupt service routine tests both the T1PND and T1C0 flags to determine the cause of the interrupt, resets the pending bit, and performs the required task, such as recording the T1RA register contents or incrementing an underflow counter.
Figure 16: Input Capture Mode
16-bit Timer Internal Bus INT A INT A
Instruction Clock
16-bit Input Capture T1RA Edge Selector Logic T1
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5.5 Mode 4: Difference Input Capture Mode
The difference capture mode is similar to the standard capture mode. The difference is the difference capture timer will automatically capture the difference between selectable edges. For example, a standard capture timer must be configured to capture a particular edge (rising or falling) at which time the timer value is copied into a capture register. If more information is required, software must move the captured data to RAM and reconfigure the capture timer to capture on the next edge (rising or falling). Software must then subtract the difference between the two edges to yield useful information. The difference capture timer eliminates the need for software intervention and allows for capturing very short pulse widths. The difference capture timer can be programmed to capture:
1. positive-edge to negative-edge 2. positive-edge to positive-edge 3. negative-edge to positive-edge 4. negative-edge to negative-edge Once configured, the difference capture timer waits for the selected edge. When an edge transition has occurred, the 16-bit timer starts counting up based on the instruction clock. It will continue to count until the second edge transition occurs at which time the timer stops and stores the elapse time into the T1RA register. Software can now read the difference between transitions directly without using any processor resources. This feature allows the ACE1202 to capture very small pulses where standard microcontrollers might have missed due to limited bandwidth
Figure 17: Difference Capture Mode
16-bit Timer Internal Bus Difference Logic
Instruction Clock
Edge Selector Logic
T1
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6.0 Timer 0
Timer 0 is a 12-bit idle timer. Upon power up or any reset, the timer is reset to 0 and then counts up continuously based on the instruction clock of 1MHz (1s). Software cannot read from or write to this timer. However, software can monitor the timer's pending (T0PND) bit which is set every 4.096ms. The T0PND is set each time the timer overflows (counts up to FFFh). After an overflow, the timer will reset and restart its count up sequence. Software can either poll the T0PND bit or vector to interrupt routine. In order to interrupt on a T0PND, software will need to make sure the interrupt enable (T0INTEN) bit is set in the T0CNTRL register and also make sure the global interrupt bit (G) is set in the status register. Once the timer interrupt is serviced, software should reset the T0PND bit before exiting the routine. The Timer 0 supports the following functions: 1. Start up delay from halt mode. 2. Watchdog prescaler. (See Section 7 for details.) The Timer 0 interrupt enable (T0INTEN) bit is a read/write bit. If set to 0, interrupt requests from the Timer 0 are ignored. If set to 1, interrupt requests are accepted. The T0INTEN bit is set to zero at reset.
The T0PND (Timer 0 pending) bit is a read/write bit. If set to "1," it indicates that a Timer 0 interrupt is pending. This bit is set by a Timer 0 overflow and is reset by software or reset. The WKINTEN bit is used in the Multi-input wakeup block. (See Section 8 for details.)
7.0 Watchdog timer
The 12-bit Timer 0 is also used to clock the watchdog timer. If the WDEN bit in the initialization register is asserted, the watchdog timer must be updated at least every 65,536 cycles but no sooner than 4096 cycles since the last watchdog update. The watchdog is updated through software by writing the value 0x1bh to the WDSVR register (see Figure 19). The part will be reset automatically if the watchdog is updated too frequently, or not frequently enough. The WDEN bit can only be set while the device is in programming mode. Once set, the watchdog will always be powered up enabled. Software cannot disable the watchdog. The watchdog timer can be disabled in programming mode by resetting the WDEN bit as long as the global write protect feature is not enabled (WDIS).
Figure 18: Timer 0 Control Register (T0CNTRL) Bit 7
WKINTEN
Bit 6
x
Bit 5
x
Bit 4
x
Bit 3
x
Bit 2
x
Bit 1
T0PND
Bit 0
T0INTEN
Figure 19: Watchdog Service Register (WDSVR) Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
1
Bit 3
1
Bit 2
0
Bit 1
1
Bit 0
1
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8.0 Multi-Input Wakeup Block
There are three memory-mapped registers associated with this circuit: WKEDG (Wakeup Edge), WKEN (Wakeup Enable), and WKPND (Wakeup Pending). Each register has eight bits, with the six least significant bits corresponding to one of the input pins shown in Figure 20. All three registers are initialized to zero with a Reset. The WKEDG register establishes the edge sensitivity for each of the port input pins: either positive-going edges (0) or negativegoing edges (1). The WKEN register enables (1) or disables (0) each of the port pins for the Wakeup/Interrupt function. Any pin to be used for the Wakeup/Interrupt function must also be configured as an input pin in the PORTGC configuration register. The WKPND register contains the pending flags corresponding to each of the port pins (1 for wakeup/interrupt pending, 0 for wakeup/interrupt not pending). The T0CNTRL register is the Timer0 control register; however, bit 7 (WKINTEN) is used as the wakeup interrupt enable bit (see Figure 18). By setting this bit the device can interrupt in the event of a multi-input wakeup (if the global interrupt bit is set). To use the Multi-Input Wakeup/Interrupt circuit, perform the steps listed below. Performing the steps in the order shown will prevent false triggering of a Wakeup/Interrupt condition. This same procedure should be used following a Reset because the Wakeup inputs will be set to high-impedence, resulting in unknown data on the port inputs. 1. Clear the WKEN register. 2. Set the WKEN bit. 3. If necessary, write to the port configuration register to change the desired port pins from outputs to inputs. 4. Write the WKEDG register to select the desired type of edge sensitivity for each of the pins used. 5. Clear the WKPND register to cancel any pending bits. 6. Set the WKEN bits associated with the pins to be used, thus enabling those pins for the Wakeup/Interrupt function. Once the Multi-Input Wakeup/Interrupt function has been set up, a transition sensed on any of the enabled pins will set the
corresponding bit in the WKPND register. This brings the device out of the HALT mode (if in that mode), and also triggers a maskable interrupt if that interrupt is enabled. The interrupt service routine can read the WKPND register to determine which pin triggered the interrupt. The interrupt service routine or other software should clear the pending bit. The device will not enter the HALT mode as long as any WKPND pending bit is pending and enabled. The user has the responsibility of clearing the pending flags before attempting to enter the HALT mode. After Reset, the WKEDG register is configured to select positivegoing edge sensitivity for all Wakeup inputs. If the user wishes to change the edge sensitivity of a port pin, use the following procedure to avoid false triggering of a Wakeup/Interrupt condition. 1. Disable the pin by clearing the associated bit in the WKEN register. 2. Write to the associated bit of the WKEDG register selecting the new edge sensitivity of the pin. 3. Clear the WKPND bit associated with the pin. 4. Re-enable the pin by setting the associated WKEN bit. PORTG provides the user with eight fully selectable, edge sensitive interrupts which are all vectored into the same service subroutine. The interrupt from PORTG shares logic with the wake up circuitry. The WKEN register allows interrupts from PORTG to be individually enabled or disabled. The WKEDG register specifies the trigger condition to be either a positive or a negative edge. The WKPND register latches the pending trigger conditions. Since PORTG is also used for exiting the device from the HALT mode, the user can elect to exit the HALT mode either with or without the interrupt enabled. If the user elects to disable the interrupt, then the device restarts execution from the point at which it was stopped (first instruction cycle of the instruction following the enter HALT mode instruction). In the other case, the device finishes the instruction which was being executed when the part was stopped (the NOP instruction following the enter HALT mode instruction), and then branches to the interrupt service routine. The device then reverts to normal operation.
Figure 20: Multi-input Wakeup (MIWU) Block Diagram Internal Data Bus
5 WKEN G0 0
0
WKOUTINT
G5
5 WKEDG WKPND
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9.0
I/O Port
The eight I/O pins are bi-directional (see Figure 21) with the exception of G3 which is always an input with weak pull-up. The bi-directional I/O pins can be individually configured by software to operate as high-impedance inputs, inputs with weak pull-up, or as push-pull outputs. The operating state is determined by the contents of the corresponding bits in the data and configuration registers. Each bi-directional I/O pin can be used for general purpose I/O, or in some cases, for a specific alternate function determined by the on-chip hardware.
9.1 I/O registers
The I/O pins (G0-G7) have three memory port registers associated with them: a port configuration register (PORTGC), a port
data register (PORTGD), and a port input register (PORTGP). PORTGC is used to configure the pins as inputs or outputs. A pin may be configured as an input by writing a `0' or as an output by writing a `1' to its corresponding PORTGC bit. If a pin is configured as an output, its PORTGD bit represents the state of the pin (1 = logic high, 0 = logic low). If the pin is configured as an input, its PORTGD bit selects whether the pin is a weak pull-up or a highimpedence input. Table 12 provides details of the port configuration options. The port configuration and data registers are both read/writeable. Reading PORTGP returns the value of the port pins regardless of how the pins are configured. Since this device supports multi-input wakeup/interrupt, PORTG inputs have Schmitt triggers.
Table 12: I/O configuration options Configuration Bit
0 0 1 1
Data Bit
0 1 0 1
Port Pin Configuration
High-impedence input (TRI-STATE output) Input with pull-up (weak one output) Push-pull zero output Push-pull one output
Figure 21: PORTG Logic Diagram
Weak Pull-up Control PORTGC PINGX PORTGD PORTGP
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10.0 In-circuit Programming Specification for ACE1202
The ACE1202 supports in-circuit programming of the internal data EEPROM, program EEPROM, and the initialization registers. An externally controlled four wire interface consisting of a LOAD control pin (G3), a serial data SHIFT_IN input pin (G4), a serial data SHIFT_OUT output pin (G2), and a CLOCK pin (G1) is used to access the on-chip memory locations. Communication between the ACE1202 and the external programmer is made through a 32-bit command and response word described in Table 13. The serial data timing for the four wire interface is shown in Figure 22. The programming protocol is shown in Figure 23. The external programmer brings the ACE1202 into programming mode by applying a supervoltage level (VSUPERVOLTAGE) to the LOAD pin. The external programmer then needs to set the LOAD pin to 5V before shifting in the 32-bit serial command word using the SHIFT_IN and the CLOCK signals. By definition, bit 31 of the command word is shifted in first. At the same time, the ACE1202 shifts out the 32-bit serial response to the last command on the SHIFT_OUT pin. It is recommended that the external programmer samples this signal tACCESS (850ns) after the rising edge of the CLOCK signal. The serial response word sent immediately after entering programming mode contains indeterminate data. After 32 bits have been shifted into the ACE1202, the external programmer must set the LOAD signal to 0V, and then apply two clock pulses as shown in Figure 23. When reading the device, the external programmer must set the LOAD signal to 5V before it sends a new command word. When writing to the ACE1202, the SHIFT_OUT signal acts as the READY signal. The ACE1202 sets SHIFT_OUT low by the time the programmer has sent the second rising edge during the LOAD = 0V phase (if the timing specifications in Figure 23 are obeyed). The ACE1202 will set the R bit of the Status register when the write operation has completed. The external programmer must wait for the R bit to go high before bringing the LOAD signal to 5V to initiate a new command cycle. Powering down the device will cause the part to exit programming mode. Writing a series of bytes to the ACE1202 is achieved by sending a series of command words with bit 24 set to 0. Reading a series of bytes from the ACE1202 is achieved by sending a series of command words with the desired addresses in sequence and reading the following response words to verify the correct address and reading the data contents. The addresses for the data EEPROM and code EEPROM spaces are the same as those used in normal operation.
Table 13: 32-Bit Command and Response Word Bit number
bits 31 - 30 bit 29 bit 28 bits 27 - 25 bit 24 bits 23 - 19 bits 18 - 8 bits 7 - 0
Input command word
Must be set to 0 Set to 1 to read/write data EEPROM, 0 otherwise Set to 1 to read/write code EEPROM, Initialization registers 0 otherwise Must be set to 0 Set to 1 to read, 0 to write Must be set to 0 Address of the byte to be read or written Data to be programmed or zero if data is to be read X X X X X X
Output response word
Same as Input command word Programmed data or data read at specified address
NOTE 1: During in-circuit programming, pin 3 (G5) must be either not connected or driven high. NOTE 2: For further information, see Application Note AN-8005.
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ACE1202 Rev. E.1
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Figure 22 - Serial Data Timing
tHI tLO
CLOCK (G1)
tDIS tDIH VALID tDOS tDOH VALID
SHIFT_IN (G4)
SHIFT_OUT (G2)
Figure 23 - Programming Protocol
tSV1 tSV2 tload1 tload2 tready tload3 + ch1*
*in read mode
tload3
tload4
12V 5V
LOAD
enter programming mode
A A: denotes start of programming cycle
32 clock pulses
A
0V
CLOCK SHIFT_IN
bit 31
bit 30
bit 0
Busy low by 2nd clock pulse
READY
SHIFT_OUT (in Write mode) SHIFT_OUT (in Read mode)
BUSY
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ACE1202 Rev. E.1
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
11.0 Low battery detect circuit
The Low Battery Detect (LBD) circuit sets the LBD bit in the LBD register (see Figure 24) when VCC drops below the selected threshold voltage. The threshold voltage can be adjusted from 2.4V to 3.0V 10% using the three most significant bits of the LBD register. The LBDEN (Low Battery Detect enable) bit in the initialization register is used to enable or disable the low battery detection. The LBD bit is read only. If 0, it indicates that the VCC level is higher than the desired threshold. If set to 1, it indicates that the VCC level is below the desired threshold. The LBD circuit is disabled during HALT mode. On exiting HALT mode, the software must wait 10s before reading the LBD bit to ensure that the circuit has stabilized.
Reset enable (BOREN) bit in the initialization register is used to enable or disable the brown-out detection. This bit must be set after the device has been programmed. Brown-out is not supported on 2.2/2.7V devices.
13.0 RESET block
When a RESET sequence is initiated, all I/O registers will be reset, setting all I/Os to high impedence inputs. The system clock is restarted after the required clock start-up delay. A reset is generated by any one of the following three conditions: I Power-on RESET (as described in Section 14) I Brown-out RESET (as described in Section 12) I Watchdog RESET (as described in Section 7)
14.0 Power-on Reset
The Power-on RESET circuit is guaranteed to work if the rate of rise of VDD is no slower than 10ms/1 volt. It is also necessary that VDD starts from 0V.
Bat_trim2 Bat_trim1 Bat_trim0
0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1
Voltage Range
2.9 - 3.0 2.8 - 2.9 2.7 - 2.8 2.6 - 2.7 2.5 - 2.6 2.4 - 2.5
15.0 CLOCK
The ACE1202 has an on-board oscillator trimmed to a frequency of 2MHz, yielding a 1MHz frequency and a tolerance over temperature, voltage, and device of 10%. Upon power-up, the onchip oscillator runs continuously unless entering HALT mode. If required, an external oscillator circuit may be used depending on the states of the CMODE bits. (See Table 14.) When the device is driven using an external clock, the clock input to the device (G1/ CKI) can range between DC to 4MHz. For crystal configuration, the output clock (CKO) is on the G0 pin. If an external crystal or external RC is used, it will be internally divided by four (input frequency/4) to yield an instruction clock cycle time of the corresponding input frequency. If the device is configured for an external square clock, it will not be divided. See Figure 26.
12.0 Brown-out detection circuit
The Brown-out detect circuit is used to reset the device when Vcc falls below a 2.0V threshold. Once VCC rises above the 2.0V threshold, a reset sequence will be generated. The Brown-out
Table 14: CMODEx Bit Definition CMODE1
0 0 1 1
CMODE0
0 1 0 1
Clock Type
Internal 1 MHz clock External square clock External crystal/resonator External RC clock
Figure 24: LBD Register Definition Bit 7
Bat_trim2
Bit 6
Bat_trim1
Bit 5
Bat_trim0
Bit 4
undefined
Bit 3
undefined
Bit 2
undefined
Bit 1
undefined
Bit 0
LBD
Figure 25: HALT Register Definition Bit 7
undefined
Bit 6
undefined
Bit 5
undefined
Bit 4
undefined
Bit 3
undefined
Bit 2
undefined
Bit 1
undefined
Bit 0
EHALT
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ACE1202 Rev. E.1
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Figure 26: Crystal (a) and RC (b) Oscillator Diagrams
a) CKI (G1) CKO (G0) b) CKI (G1) CKO (G0)
1M R VCC C 33pF 33pF
16.0
HALT Mode
The ACE1202 is placed into HALT by setting bit 0 of the HALT mode register using the LD M, # instruction. The HALT enable bit (Bit 0) is a write only bit and is automatically cleared on exiting halt. Upon entering HALT, the internal oscillator, as well as all on-chip systems, including Low battery detect and Brown out circuits, are shut down. Prior to entering HALT, software should set the
appropriate wake-up I/O configuration. The device can only be brought out of HALT by multi-input wake up. After wake up from HALT, a 1ms startup delay is initiated to allow the internal oscillator to stabilize before normal execution resumes. Immediately after exiting HALT, software must clear the Power mode clear register also using a LD M, # instruction. See Figure 27 below.
Figure 27: Recommended HALT Flow
Normal Mode
LD HALT, #01h
Halt
Multi-Input Wakeup
LD PMC, #00h
Resume Normal Mode
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ACE1202 Rev. E.1
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Ordering Information ACE 12 02 X E MT8 X Letter
X Package M8 M N N14 None E V None B L
Description
Tape and Reel 8-pin SO 14-pin SO 8-pin DIP 14-pin DIP 0 to 70C -40 to +85C -40 to +125C 2.2V - 5.5V 2.7V - 5.5V 2.0V - 5.5V
Temp. Range
Operating Voltage Range
Density
02 12 ACE
2K Code EEPROM 8-bit Microcontroller Core Type Arithmetic Controller Engine
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ACE1202 Rev. E.1
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197 (4.800 - 5.004)
8765
0.228 - 0.244 (5.791 - 6.198)
1234
Lead #1 IDENT 0.150 - 0.157 (3.810 - 3.988) 8 Max, Typ. All leads 0.04 (0.102) All lead tips
0.010 - 0.020 x 45 (0.254 - 0.508)
0.053 - 0.069 (1.346 - 1.753)
0.004 - 0.010 (0.102 - 0.254) Seating Plane
0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads
0.016 - 0.050 (0.406 - 1.270) Typ. All Leads
0.014 (0.356) 0.050 (1.270) Typ 0.014 - 0.020 Typ. (0.356 - 0.508)
Molded Small Out-Line Package (M8) Order Number ACE1202M8/ACE1202EM8/ACE1202VM8 Package Number M08A
0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) 0.092 DIA (2.337) Pin #1 IDENT Option 1
8
+
7
6
5
0.250 - 0.005 (6.35 0.127)
0.032 0.005 (0.813 0.127) RAD Pin #1 IDENT
8
7
1 1 2 3 4
0.039 (0.991) 0.130 0.005 (3.302 0.127) Option 2 0.145 - 0.200 (3.683 - 5.080)
0.280 MIN (7.112) 0.300 - 0.320 (7.62 - 8.128)
0.040 Typ. (1.016) 0.030 MAX (0.762) 20 1
95 5 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 0.125 (3.175) DIA NOM
0.065 (1.651)
0.125 - 0.140 (3.175 - 3.556) 90 4 Typ 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.060 (1.524)
0.020 (0.508) Min
0.045 0.015 (1.143 0.381) 0.050 (1.270)
Molded Dual-In-Line Package (N) Order Number ACE1202N/ACE1202EN/ACE1202VN Package Number N08E
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ACE1202 Rev. E.1
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Physical Dimensions inches (millimeters) unless otherwise noted
0.335 - 0.344 (8.509 - 8.788)
14 13 12 11 10 9
8
0.228 - 0.244 (5.791 - 6.198)
0.010 Max. (0.254)
1
Lead #1 IDENT
0.150 - 0.157 (3.810 - 3.988)
2
3
4
5
6
7
30 Typ.
0.010 - 0.020 x 45 (0.254 - 0.508)
8 Max, Typ. All leads 0.04 (0.102) All lead tips
0.053 - 0.069 (1.346 - 1.753)
0.004 - 0.010 (0.102 - 0.254)
Seating Plane 0.016 - 0.050 (0.406 - 1.270) Typ. All Leads 0.014 (0.356) 0.050 (1.270) Typ 0.014 - 0.020 Typ. (0.356 - 0.508) 0.008 Typ (0.203)
0.008 - 0.010 (0.203 - 0.254) Typ. all leads
Molded Small Out-Line Package (M) Order Number ACE1202M/ACE1202EM/ACE1202VM Package Number M14A
Molded Dual-In-Line Package (N14) Order Number ACE1202N14/ACE1202EN14/ACE1202VN14 Package Number N14A
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ACE1202 Arithmetic Controller Engine (ACExTM) for Low Power Applications
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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